1.1 Hardware

  The processor modules are RIO2 8060 boards from CES. Their main components are:

• a 100 MHz PowerPC-604 processor with on-chip $2\; 8$ Kbytes cache
• 8 Mbyte of on-board DRAM memory
• PCI standard backbone bus (bandwidth 128 Mbytes/s)
• IBM Lanaï/Kauaı Bridge chipset for interfacing the CPU subsystem to the memory
• VME D64 Master/Slave interface

The modules house two custom-built PCI mezzanines that carry 4 FADCs each. The analogue data are fed onto the PMCs via front panel connectors. One PowerPC processes the data of $8\; 1280\; =\; 10240$ readout strips. Communication with the H1 trigger system is established via a modified VME backplane.

In total, 8 RIO boards for the CST and 8 for the BST are used. In the Silicon VME taxi ring, they are placed into crate no. 3. Future expansions will establish a second RIO crate (no. 4). CST and BST will then use different crates and one of them will host the four VLQ RIO boards.