The decoder chip (1.2 
2.4 mm 
) is built in SACMOS 1 technology
(1.2 
m feature size) [13].
It is placed on each face of the
hybrid and generates various control bit patterns applied to
the APC128 chip. In addition it performs
some slow control functions and allows calibrations.
Bit patterns can be loaded sequentially into a 64 bit shift
register through one data line and using two clocks and one control line
(see figure 5). The first four bits serve for internal control
of the chip. Bits 5 through 11 generate seven signal levels applied to the APC128.
The next five bits are available for other purposes. 32 lines are reserved for the
Calibrate Register, eight bits for the Slow Control Register and seven
signals for the Current Supply Register. The last bit allows, if
connected, to choose a feedback resistor value of the APC128 preamplifiers,
that is either lower (bit low) or higher (bit high) than the default
resistor value.
The electronics for the n-side of the DC-coupled sensors has to operate at the bias voltage. The four input lines for the decoder have therefore to be AC-coupled. In our solution the input comparators on the decoder chip (figure 6) have two stable states and switch from a high output state to a low output state and vice versa with an input signal difference of 600 mV through coupling capacities of only 15 pF. For system uniformity the inputs to the decoder chip for the p-sides are also AC-coupled.