The decoder chip runs in two main modes of operation
which are selected with the switch
OUT/SR (see figure 5). In the mode OUT the input signals
BIN (bit-in), Clk1 (clock1) and Clk2 (clock2) are, depending on the
value of bit 1 of the shift register, directly
connected to the outputs 
or 
,
or 
, and SBI or RBI, corresponding to the
Sampling Phase (operating the pipeline shift register of the APC128),
or the Readout Phase. The second mode SR is
the downloading of the 64 bit shift register of the decoder.
In this case the switch OUT/SR is
in the position SR (Shift Register) and the signal BIN is shifted
into the register using the clocks
Clk1 and Clk2. The cycle frequency is kept at 10 MHz for sampling
and downloading, and 2 MHz for readout, respectively.
The decoder also allows routing of the readbit-in (RBI) signal. In our case the input RBE (readbit enable) is hard-wired to either one of two available bits and operates a switch which enables or inhibits the RBI signal. In this way two p-sides (n-sides) can be read out successively through the same readout channel.