The central silicon tracker of H1 consists of two
coaxial layers of 12 and 20
silicon ladders with an active length of 35.8 cm. The first half shell
has been installed in H1 for the
1995 running period (figure 1). The sensors [11] are
double sided, with 640 DC-coupled readout lines on each side.
Hybrids made from 
carry on both faces five APC128 chips and the pertinent control
circuit with an ASIC Decoder Chip as the center piece (figure 2).
Figure 3 shows the electrical and
optical system layout. Signals from the silicon sensors are
amplified and stored in the switched capacitor pipeline of the APC128 chip,
see figure 4) [7]. The pipeline is
continuously operated with the HERA clock of 10.4 MHz until a trigger signal
arrives and stops it. During the subsequent readout the pipeline buffer of the
corresponding time slice of each channel is connected sequentially to the output
amplifier, brought via a 5 cm long flat and flexible Kapton cable to a printed circuit
at the end of the detector and
converted into optical signals. Two p-sides (n-sides) of two adjacent half-ladders
are daisy-chained and connected to a single fiber which transmits 1280 channels
per event. The reconverted
signals are digitised in the Online Silicon Readout Controler
(OnSiRoc) [12].
The control signals for the APC128 are generated in the decoder chip. For each mode of operation of the APC128 a specific bit sequence is loaded into the 64 bit decoder chip shift register (figure 5). This bitstream is prepared in a sequencer in the (OnSiRoC) [12] located outside the experiment some 34 m away. Since all APC128 chips need at any given time the same control sequence, all decoder registers can be loaded simultaneously via four optical lines.