The Trigger Card Status Word

Is read with every event and placed into the SITR bank.

Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
bsy ini - sie so3 so2 so1 so0 rse spe si3 si2 si1 si0 rhe rhi

where:

Note that only the bsy and ini bits are of any relevance for the data at the time being! The spare in/out system has been used for test purposes only (and is not available in the STC due to the lack of custom vme access).

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© by Hans Henschel, 14-sep-96, last revised: 26-aug-98