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10. OnSiRoC Registers and Offsets
This section lists the registers and offsets with their acronyms as used in the SiVMEXI package.
The programmer should always refer to the most recent version of the OnSiRoC manual for any changes [9].
Offsets
SICTRLREG EQU $04 ; Control Register 1 + 2 (32-bit, Write)
SIRAW13 EQU $08 ; Raw Data Memory 1 + 3 (32-bit, Read/Write)
SIRAW1 EQU $0A ; Raw Data Memory 1 (16-bit, Read/Write)
SIRAW3 EQU $08 ; Raw Data Memory 3 (16-bit, Read/Write)
SIRAW24 EQU $0C ; Raw Data Memory 2 + 4 (32-bit, Read/Write)
SIRAW2 EQU $0E ; Raw Data Memory 2 (16-bit, Read/Write)
SIRAW4 EQU $0C ; Raw Data Memory 4 (16-bit, Read/Write)
SIFADC13 EQU $10 ; FADC 1 + 3 (32-bit, Read)
SIFADC24 EQU $14 ; FADC 2 + 4 (32-bit, Read)
SIFCLK1 EQU $18 ; FADC Clock 1 (16-bit, Write)
SIFCLK2 EQU $1A ; FADC Clock 2 (16-bit, Write)
SIFCLK3 EQU $1C ; FADC Clock 3 (16-bit, Write)
SIFCLK4 EQU $1E ; FADC Clock 4 (16-bit, Write)
SIPED EQU $20 ; Pedestal Memory 1+2+3+4 (32-bit, Read/Write)
SIPED1 EQU $23 ; Pedestal Memory 1 ( 8-bit, Read/Write)
SIPED2 EQU $22 ; Pedestal Memory 2 ( 8-bit, Read/Write)
SIPED3 EQU $21 ; Pedestal Memory 3 ( 8-bit, Read/Write)
SIPED4 EQU $20 ; Pedestal Memory 4 ( 8-bit, Read/Write)
SIPEDCC1IN EQU $24 ; Pedestal Memory CC1 Inc (32-bit, Read/Write)
SICC2PIC EQU $28 ; Channel+Pipeline Countr2 (32-bit, Read/Write)
SICC2 EQU $2A ; Channel Counter 2 (16-bit, Read/Write)
SICC2IN EQU $2C ; Channel Counter 2 Inc (16-bit, Write)
SIPICIN EQU $2E ; Pipeline Counter Inc (16-bit, Write)
SISEQ EQU $30 ; Sequencer Memory (32-bit, Read/Write)
SISEQ12 EQU $34 ; Sequencer Address 1 + 2 (32-bit, Write)
SISEQ3 EQU $38 ; Sequencer Address 3 (16-bit, Write)
SISEQCLK EQU $3A ; Sequencer Clock (16-bit, Write)
SIFCLK EQU $3C ; FADC Clock 1+2+3+4 (16-bit, Write)
SIHDTHRESH EQU $40 ; Hit Detector Threshold (32-bit, Read/Write)
SIHDWIDTH EQU $46 ; Hit Detector Width (16-bit, Read)
SIHDSETCLK EQU $48 ; Hit Detector Set+Clock (32-bit, Write)
SIHDRES12 EQU $4C ; Hit Detector Reset 1 + 2 (16-bit, Write)
SIHDRES34 EQU $4E ; Hit Detector Reset 3 + 4 (16-bit, Write)
SIHDRES EQU $50 ; Hit Det Reset 1+2+3+4 (16-bit, Write)
SICLUSTER EQU $52 ; Cluster Det. Threshold (16-bit, Read/Write)
SIPC13 EQU $54 ; Pointer Counter 1 + 3 (32-bit, Read/Write)
SIPC1 EQU $56 ; Pointer Counter 1 (16-bit, Read/Write)
SIPC3 EQU $54 ; Pointer Counter 3 (16-bit, Read/Write)
SIPC24 EQU $58 ; Pointer Counter 2 + 4 (32-bit, Read/Write)
SIPC2 EQU $5A ; Pointer Counter 2 (16-bit, Read/Write)
SIPC4 EQU $58 ; Pointer Counter 4 (16-bit, Read/Write)
SIPCIN13 EQU $5C ; Ptr Ctr Increment 1 + 3 (16-bit, Write)
SIPCIN24 EQU $5E ; Ptr Ctr Increment 2 + 4 (16-bit, Write)
SIPCIN EQU $60 ; Ptr Ctr Inc 1+2+3+4 (16-bit, Write)
SIPCRES13 EQU $62 ; Ptr Ctr Reset 1 + 3 (16-bit, Write)
SIPCRES24 EQU $64 ; Ptr Ctr Reset 2 + 4 (16-bit, Write)
SIPCRES EQU $66 ; Ptr Ctr Reset 1+2+3+4 (16-bit, Write)
SIPOINT13 EQU $68 ; Pointer Memory 1 + 3 (32-bit, Read/Write)
SIPOINT1 EQU $6A ; Pointer Memory 1 (16-bit, Read/Write)
SIPOINT3 EQU $68 ; Pointer Memory 3 (16-bit, Read/Write)
SIPOINT24 EQU $6C ; Pointer Memory 2 + 4 (32-bit, Read/Write)
SIPOINT2 EQU $6E ; Pointer Memory 2 (16-bit, Read/Write)
SIPOINT4 EQU $6C ; Pointer Memory 4 (16-bit, Read/Write)
SICLKSTART EQU $70 ; Clock Loop Start (16-bit, Write)
SICLKSTOP EQU $72 ; Clock Loop Stop (16-bit, Write)
SICLKRES EQU $74 ; Clock Divider Reset (16-bit, Write)
SIFCLEAR EQU $76 ; Fast Clear (16-bit, Write)
SIL2KEEP EQU $78 ; L2-Keep (16-bit, Write)
SIL2REJECT EQU $7A ; L2-Reject (16-bit, Write)
SIL2DRES EQU $7C ; L2-Delay Reset (16-bit, Write)
SIFERRES EQU $7E ; Front-Ends Ready Reset (16-bit, Write)
SIINTSET EQU $80 ; Interrupter Set (16-bit, Write)
SIINTCLR EQU $82 ; Interrupter Clear (16-bit, Write)
SICRESR12 EQU $84 ; Card Reset with reg 1+2 (16-bit, Write)
SICRESWR1 EQU $86 ; Card Reset without reg 1 (16-bit, Write)
SICRESWR2 EQU $88 ; Card Reset without reg 2 (16-bit, Write)
SICRESWR12 EQU $8A ; Card Reset without reg1+2(16-bit, Write)
SIBVC1 EQU $90 ; Bias Voltage/Current 1 (16-bit, Read/Write)
SIBVC2 EQU $92 ; Bias Voltage/Current 2 (16-bit, Read/Write)
SIBVC3 EQU $94 ; Bias Voltage/Current 3 (16-bit, Read/Write)
SIBVC4 EQU $96 ; Bias Voltage/Current 4 (16-bit, Read/Write)
SICPED1 EQU $98 ; Coarse Pedestal 1 (16-bit, Read/Write)
SICPED2 EQU $9A ; Coarse Pedestal 2 (16-bit, Read/Write)
SICPED3 EQU $9C ; Coarse Pedestal 3 (16-bit, Read/Write)
SICPED4 EQU $9E ; Coarse Pedestal 4 (16-bit, Read/Write)
SISTATUS EQU $A2 ; Status Register Offset (16-bit, Read)
SIRAWCC2IN13 EQU $A4 ; Raw Data Mem 1 + 3 CC Inc(32-bit, Read/Write)
SIRAWCC2IN24 EQU $A8 ; Raw Data Mem 2 + 4 CC Inc(32-bit, Read/Write)
SIPOINTIN13 EQU $AC ; Pointer Mem 1 + 3 PC Inc (32-bit, Read/Write)
SIPOINTIN24 EQU $B0 ; Pointer Mem 2 + 4 PC Inc (32-bit, Read/Write)
SIPEDPICIN EQU $B4 ; Pedestal Memory PIC Inc (32-bit, Read/Write)
SIPRAWIN1 EQU $B8 ; Pointer + Raw Mem 1 + Inc(32-bit, Read/Write)
SIPRAWIN2 EQU $BC ; Pointer + Raw Mem 2 + Inc(32-bit, Read/Write)
SIPRAWIN3 EQU $C0 ; Pointer + Raw Mem 3 + Inc(32-bit, Read/Write)
SIPRAWIN4 EQU $C4 ; Pointer + Raw Mem 4 + Inc(32-bit, Read/Write)
SICC1PIC EQU $C8 ; Channel+Pipeline Countr1 (32-bit, Read/Write)
SICC1 EQU $CA ; Channel Counter 1 (16-bit, Read/Write)
SICC1RES EQU $CC ; Channel Counter 1 Reset (16-bit, Write)
SICC2RES EQU $CE ; Channel Counter 2 Reset (16-bit, Write)
SICC12RES EQU $D0 ; Channel Counter 1+2 Reset(16-bit, Write)
SICC1INC EQU $D2 ; Channel Counter 1 Inc (16-bit, Write)
SIPICRES EQU $D4 ; Pipeline Counter Reset (16-bit, Write)
SICCPICRES EQU $D6 ; CC+Pipeline Counter Reset(16-bit, Write)
OnSiRoC Control Register bits
Ctrl Reg 1
SI_PEN EQU 0 ; PEN*
SI_CLKINT EQU 1 ; CLKINT
SI_PI_ON EQU 2 ; PION
SI_PIOFF EQU 3 ; PIOFF
SI_FCOFF EQU 4 ; FCOFF
SI_FEREN EQU 5 ; FEREN*
SI_L2OFF EQU 6 ; L2OFF
SI_L2AUTO EQU 7 ; L2AUTO
SI_CSEN EQU 8 ; CSEN*
SI_IRMOD1 EQU 9 ; IRMOD1
SI_IRMOD2 EQU 10 ; IRMOD2
SI_IRD0 EQU 11 ; IRD0
SI_IRD1 EQU 12 ; IRD1
SI_IRD2 EQU 13 ; IRD2
SI_IRD3 EQU 14 ; IRD3
SI_IRD4 EQU 15 ; IRD4
Ctrl Reg 2
SI_PSON11 EQU 16 ; PSON1.1*
SI_PSON12 EQU 17 ; PSON1.2*
SI_PSON13 EQU 18 ; PSON1.3*
SI_PSON14 EQU 19 ; PSON1.4*
SI_PSON21 EQU 20 ; PSON2.1*
SI_PSON22 EQU 21 ; PSON2.2*
SI_PSON23 EQU 22 ; PSON2.3*
SI_PSON24 EQU 23 ; PSON2.4*
SI_PSON31 EQU 24 ; PSON3.1*
SI_PSON32 EQU 25 ; PSON3.2*
SI_PSON33 EQU 26 ; PSON3.3*
SI_PSON34 EQU 27 ; PSON3.4*
SI_SITP1 EQU 28 ; SITP1
SI_SITP2 EQU 29 ; SITP2
SI_SITP3 EQU 30 ; SITP3
SI_SITP4 EQU 31 ; SITP4
OnSiRoC Status Register bits
SI_CLKON EQU 0 ; Bit 0 Clock On. CLKON
SI_PION EQU 1 ; Bit 1 Pipeline On. PION
SI_L2PON EQU 2 ; Bit 2 L2-Keep Prompt On. L2PON
SI_L2DON EQU 3 ; Bit 3 L2-Keep Delay On. L2DON
SI_FERDISP EQU 4 ; Bit 4 Front-End Ready On. FERDISP*
SI_ADRDY EQU 5 ; Bit 5 ADC Ready. ADRDY
SI_IRON EQU 6 ; Bit 6 Interrupt On. IRON
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