130 secondsnxt 28.08.98 - 0:47 "4bit counter @ H1clock; 12bit counter @ 18Hz" HH Test BOS structure errors
made to traceback BOS structure errors in the TSCD readout
129 seconds 27.08.98 - 23:59 "5bit counter w/ H1clock & 11bit counter w/ 0.5Hz" HH don't use!
wrong file format, due to version change in the development system!
128 count2 07.07.98 - 10:20 "just a counter in each Xilinx" HH don't use!
wrong file format, due to version change in the development system!
127 mapscx5 30.06.98 - 16:09 "as mapscx; bitgen formatting updated" HH don't use!
wrong file format, due to version change in the development system!
126 mapscx4 21.06.98 - 6:15 "next try" HH don't use!
wrong file format, due to version change in the development system!
125 mapscx31 21.06.98 - 6:10 "next try" HH don't use!
wrong file format, due to version change in the development system!
124 mapscx3 21.06.98 - 5:36 "as mapscx1 but run=PEN not connected" HH don't use!
wrong file format, due to version change in the development system!
123 thru3t3notrx 27.04.1998 - 17:23 "pulses disk3 when NOT run" HH
122 thru2t2notrx 27.04.1998 - 17:23 "pulses disk2 when NOT run" HH
121 thru1t1notrx 27.04.1998 - 17:23 "pulses disk1 when NOT run" HH
120 thru0t0notrx 27.04.1998 - 17:22 "pulses disk0 when NOT run" HH
119 count 02.09.97 - 0:50 "simple counter 8*16bit linked" HH
118 sync4_56 16.05.97 - 10:24 "sync middle 4 rings MAP disk5&6; no tp" HH
117 sync4_2M 14.05.97 - 11:47 "as sync4-1M" HH
116 sync4_1M 22.04.97 - 11:17 "disk5 sync thru; no tp; MAP" HH
file lost!
114 bstpad8 13.03.97 - 0:17 "full trigger design for sector 8 without tp." WA
sector 8 full logic: sync; 47 masks & encoding; multiplicity; qualifiers
113 s43rr 11.03.97 - 22:01 "real signals from disc3 with decode" WA
disc 3 sync thru ring-wise sorted; no testpulse
112 s42rr 10.03.97 - 23:00 "real signals from disc2 with decode" WA
disc 2 sync thru ring-wise sorted; no testpulse
111 s41rr 10.03.97 - 23:00 "real signals from disc1 with decode" WA
disc 1 sync thru ring-wise sorted; no testpulse
110 memtp 10.03.97 - 22:59 "almost final design with tp. 2-24" WA
sector 8 full logic: sync; 47 masks & encoding; multiplicity; qualifiers; testpulse 2:24
109 bsts3 08.03.97 - 19:45 "as bstx3, but with changed sync. block" WA
sync masks & async hardwired 97'masks; no testpulse (cf. bstx3)
108 sync43r 05.03.97 - 11:52 "wiring'97, comp. sync. and unsync., ohne tp. disc 7" WA
disc 3 sync thru channel-wise; no testpulse
107 bst34-2 06.03.97 - 11:26 "again revised version of bst32" HH
sync & 97'hardwired masks (no macro!) for old system; testpulses 2:24; 4th repeater not used for clocking
106 sync42r 05.03.97 - 11:52 "new branch. without tp. disk 6" WA
disc 2 sync thru channel-wise; no testpulse
105 sync41r 05.03.97 - 11:52 "new branch. without tp." WA
disc 1 sync thru channel-wise; no testpulse
104 bstx3 05.03.97 - 23:44 "wiring97, comp. sync. and. unsync. without tp." WA don't use!
sync masks & async hardwired 97'masks; no testpulse sync block probably wrong
103 bst35 05.03.97 - 12:16 "as bst3i, but new wiring & tp 2-24" WA
hardwired masks synchronized through; testpulse every 24 bc.s, 2 clock wide
102 bst34 05.03.97 - 11:47 "as bst 33; corrected for not cabled 4th repeater" HH
sync & 97'hardwired masks for old system; testpulses 2:24; 4th repeater not used for clocking no response from some sectors
101 bst33 27.02.97 - 14:58 "hardwired masks for old branch & tp" HH
sync & 97'hardwired masks for old system; testpulses 2:24 repeater 4 requires clocking!
100 bst32 25.02.97 - 1:24 "hardwired tracks for '97 setup, sync, tp 2:24" HH no response?
97 corrected masks synchronized through; testpulse every 24 bc.s, 1 clock wide, shown on bit 7 sectors 4/5 showed no testpulse?
99 sync43-3 20.02.97 - 0:05 "disk3 sync4ff thru; tp @ 'x8' inverted" HH no response to testpulses?
disk 3 inputs synchronized (standard 4 FFs); testpulse every 24 bc.s, 2 clocks long € inverted!
98 bst3i2 19.02.97 - 20:37 "selected channels thru; sync4ff; tp 2:24 on bit 7" HH no response?
hardwired masks synchronized through; testpulse every 24 bc.s, 1 clock wide, shown on bit 7 sectors 4/5 showed no testpulse?
97 sync4w3-2 19.02.97 - 19:41 "disk3 sync4ff; tp@count 'x8' (x odd)" WA use for threshold runs
disk 3 inputs synchronized (standard 4 FFs); testpulse every 24 bc.s, 2 clocks long response 1 to 3 bc.s after testpulse
96 sync4w2-2 19.02.97 - 19:00 "disk2 sync4ff; tp @ count 'x8' (x odd)" WA use for threshold runs
disk 2 inputs synchronized (standard 4 FFs); testpulse every 24 bc.s, 2 clocks long response 1 to 3 bc.s after testpulse
95 sync4w1-2 19.02.97 - 19:00 "disk1 sync4ff; tp @ count 'x8' (x odd)" WA use for threshold runs
disk 1 inputs synchronized (standard 4 FFs); testpulse every 24 bc.s, 2 clocks long response 1 to 3 bc.s after testpulse
94 sync4w1 19.02.97 - 12:15 "disk1 thru; sync4ff; tp 1:24" WA do not use!
trial
93 thru3tp3x 14.02.97 - 13:01 "disk 3 through; testpulse 1:32" HH no response seen -> sync!
disk 3 direct through, testpulse every 32 bc.s
92 thru2tp2x 14.02.97 - 13:04 "disk 2 through; testpulse 1:32" HH no response seen -> sync!
disk 2 direct through, testpulse every 32 bc.s
91 thru1tp1x 14.02.97 - 13:08 "disk 1 through; testpulse 1:32" HH no response seen -> sync!
disk 1 direct through, testpulse every 32 bc.s
90 thru0tp0x 14.02.97 - 13:11 "disk 0 through; testpulse 1:32" HH dummy (no detector there)
disk 0 direct through, testpulse every 32 bc.s
89 mapscx1 14.02.97 - 10:37 "as mapscx but pinning mirrored" HH Standard Prague Mapping
counts up, adjacent sectors displaced by 7; common reset; bit count corrected! use for TSCD mapping!
88 mapscx 13.02.97 - 16:33 "sector shifted (by 7) counters" HH Mapping test for Prague Rpt
counts up, adjacent sectors displaced by 7; common reset use for TSCD mapping
87 mapsc 13.02.97 - 16:23 "sector shifted (by 3) counters" HH Mapping Test for Old System
counts up, adjacent sectors displaced by 3; common reset use for TSCD mapping
86 mapc3 16.12.96 - 12:01 "16bit shiftreg" HH Function & Mapping Test
16bit shift register built from 2 sectors use @ H1 clock for online monitoring!
85 thru3t3x 06.01.97 - 13:45 "test in HH" HH Function Test for Prague Rpt
direkt through for all inputs, testpulse with RUN=1 on disc 3 use for full chain Thru Test
84 thru2t2x 06.01.97 - 13:44 "test in HH" HH Function Test for Prague Rpt
direkt through for all inputs, testpulse with RUN=1 on disc 2 use for full chain Thru Test
83 thru1t1x 06.01.97 - 13:41 "HH test3" HH Function Test for Prague Rpt
direkt through for all inputs, testpulse with RUN=1 on disc 1 use for full chain Thru Test
82 mapc4x 06.01.97 - 11:41 ".x mit x versehen" HH Channel Test
as mapc3 - but for Prague repeater (changed channel mapping, counter instead of shiftreg)
81 thru0t0x 06.01.97 - 13:42 "HH test1" HH Function Test for Prague Rpt
direkt through for all inputs, testpulse with RUN=1 on disc 0 use for full chain Thru Test
80 maps1 28.11.96 - 16:59 "as maps but left link input zeroed!" HH signature test for all sectors
same as 'maps' but the left open-end links are now tied to GND -> also sector0 counter is ok. (sect.2 Ý; sect.3 clocked via link)
79 bst-int 18.11.96 - 11:57 "new sync input - arkadov" WA
78 bst-adv2 15.11.96 - 12:44 "advanced sync. input 2 & advanced output 2" WA sector 3 not clocked
77 bst-adv 14.11.96 - 18:06 "advanced sync. input & advanced output" WA don't use!
76 sync4-adv 07.11.96 - 0:25 "as sync4-3, but with applying of an advanced synchr. " WA
75 bst3c 31.10.96 - 23:27 "sees everything" WA
74 sync4-3 31.10.96 - 12:36 "trial to revive sector 2 and 3" HH
file lost!
72 mapl8 28.10.96 - 13:54 "linktest l-to-r w/ linked clocks" HH test for sectors 2/3
71 mapc2 19.10.96 - 14:09 "shift registers, being filled from chan 0 to 6, X2/3 clocked from HH test processing channel map
intended to check channel map in histogramming
70 mapl7 18.10.96 - 17:28 "as mapl6 but link handed through X2/3" HH test sectors 2 & 3
69 mapl6 18.10.96 - 16:41 "4bit counters; 4bit links left-to-right; X2/3 clocked by X1" HH test sectors 2 & 3
life test for X2/X3 (less sphisticated)
68 mapl5 18.10.96 - 12:15 "as mapl4, but X2 & X3 with clocks provided from X1 & X4 resp." HH test sectors 2 & 3
life test for X2/X3 (X3 having no own clock)
67 maps 27.09.96 - 11:22 "what the hell is that" HH test sectors 2 & 3
5bit counter each sector, gated by link L-to-R of upper 4bit; sect.1 provides clk & gate for sect.2 & reads back its lower 2bits; sect.4 respectively for sect.3
66 mapl4 26.09.96 - 16:58 "what the hell is this" HH link test improved
4bit counters & 4bit links from right to left in each sector
65 sync11 20.09.96 - 16:24 "as sync1; bug in some delay lines removed" HH phase shift test
64 mapl2-2 19.09.96 - 16:42 "test links over all sectors from right to left" ? link functionality test
4bit counter in X7, outputs passed through links all over phi, 4bit output on each XILINX
63 bst3+i 09.09.96 - 8:22 "bst3, testpulse bug removed" HH standard running w/ testpulse
as bst3+ but testpulse generator inverted: pulses now when rh=0
62 mapl2 24.07.96 - 15:13 "no comment" ?
61 mapm2 30.08.96 - 16:44 "no comment" HH
counting signatures for link test & channel map inclusive, see appendix for analysis!
60 sync1 26.08.96 - 14:00 "?? test hans" HH Test phase shift
inverted single inputs; 8-ch 4flop latch © WA; stb 7fold delayed appr. 15ns; tp & X6/7 as #58
59 sync4e 09.08.96 - 11:50 "direct & 4 flop sync; sync out; tp" HH Test synchronization
inverted inputs; 4-ch direct through; 4-ch 4flop latch © WA & outputs latched; tp, X6 and X7 as #58
58 sync4 09.08.96 - 11:50 "direct & 4 flop sync; tp" HH Test synchronization
inverted inputs; 4-ch direct through; 4-ch 4flop latch © WA; tp generated in X6; X6: 8-ch count, tp 4:256; X7: 8-ch count, enab when X6 > 128
57 bst3e+ 19.07.96 - 10:12 "sync in/outputs & mask; testpulse 1:256" HH BST1 running std.
inverted inputs; 4flop latch © WA; 4-ch direct through; latched outputs; BST1 mask set out5; rh & sprin out6/4; rh=1 -> tp 256:1 out7
56 bst3+ 19.07.96 - 10:12 "sync inputs & mask; testpulse 1:256" HH
inverted inputs; 4flop latch © WA; 4-ch direct through; BST1 mask set out5; rh & sprin out6/4; rh=1 -> tp 256:1 out7
55 mapl 19.07.96 - 10:12 "test links w/ counters" HH test XILINX sector links
54 bst3e 17.07.96 - 10:25 "as bst3 but outputs latched" WA don't use!
53 mapmm 18.07.96 - 12:15 "as mapm, odd xilinxs mirrored" HH
52 mapm 18.07.96 - 11:23 "4bit count patterned. incl. links" HH
51 bst3i 17.07.96 - 18:11 "as bst2 but input sync (4ffs)" WA
50 mapi 17.07.96 - 14:53 "counters w/ sector carry & offset" WA
49 map 17.07.96 - 10:26 "counters w/ sector carry & offset" HH
48 bst3 17.07.96 - 10:25 "like bst2 but sync" WA don't use!
47 bst2 25.04.96 - 17:32 "test with trigger card - long test pulse" WA
46 bst1b 25.04.96 - 15:22 "bst1 corrected" HH
45 bst1a 25.04.96 - 13:29 "bst1 corrected" HH
44 bst1m 18.04.96 - 16:27 "bst1-96 masken multipl testpulses" HH
43 bst1 14.03.1996 - 19:29 "bst1 masks - sectors 0Š3" HH
42 rptrv_thru2t2i 11.03.1996 - 16:52 "same as 2t2; but tp invertable w/ spare" HH
41 rptrv_thru1t1i 11.03.1996 - 16:49 "same as 1t1; but tp invertable w/ spare" HH
40 rptrv_thru0t0i 11.03.1996 - 16:47 "same as 0t0; but tp invertable w/ spare" HH
39 rptrv_thru3t3i 11.03.1996 - 16:54 "same as 3t3 but tp with SPARE invertable" HH
38 rptrv_thru1t1+ 10.03.1996 - 14:54 "detector1 through; tp1 switched by RUN/HOLD" HH
37 rptrv_thru2t2+ 10.03.1996 - 14:56 "detector2 through; tp2 switched by RUN/HOLD" HH
36 rptrv_thru1t1+ 10.03.1996 - 14:54 "detector1 through; tp1 switched with RUN/HOLD" HH
35 rptrv_thru2t2+ 10.03.1996 - 14:56 "detector2 through; tp2 switched with RUN/HOLD" HH
33 rptrv_thru3t3 09.03.1996 - 12:09 "detector3 through; tp3 switched by RUN/HOLD" HH
30 rptrv_thru0t0 09.03.1996 - 12:23 "detector0 through; tp0 switched by RUN/HOLD" HH
29 rptrv_cnttp 07.02.1996 - 10:30 "counter & pulser, both controls valid" HH
5 rptrv_us_cntnr 14.11.1995 - 21:05 "reversed outputs" US
4 rptrv_us_cntn 13.11.1995 - 18:18 "counts while " US
3 rptrevturn 10.11.1995 - 18:22 "no comment" HH