The discriminated detector signals have to be synchronized to the H1 clock before they may undergo any data processing, namely track finding, in order to remove possible individual phase shifts.
A primitive means for synchronization is to sample the input signal with
each active clock transition, e.g. every 96 ns.
Since the peaking time of the Pad preamplifier is 46 ns however and the simple
threshold discrimination will introduce additional jitter a more
sophisticated synchronization is implemented:
Any input signal active transition will be latched individually until
getting registered with the subsequent H1 clock cycle. By providing two
paralleled latches for each input which are cleared alternating there is
basically no deadtime.
The synchronization stage is implemented in the XILINX logic on the repeater and thus reconfigurable.
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© by Hans Henschel, 10-sep-96, last revised: 18-jun-98