XILINX Download - Expert Page

The XILINX FPGAs used in the frontend electronics comprise a bulk of several thousands of logic gates which have to be configured after power-on. The Pad Detector slow control system uses the 'bit serial' protocol, where configuration data are passed to the XILINX through a single line along with a clock and control signal. A small XILINX chip housed in the PDS module serves as master whereas up to 8 XILINXs of neighboured repeaters as slaves in a daisy chain. The configuration data of each XILINX may be individual - the appropriate files of approx. 64kBits each are simply appended. Once one of the devices is done data are passed to the succeeding ones through a 'phi bridge' between adjacent repeaters.

The data stream format of the download file is as follows:

Back to the Shift Instructions. To the BST site.